Nvidia is looking for an ASIC Design Engineer.
The NVIDIA Clocks group is looking for a top ASIC engineer with inclination in high-speed logic design. The complexity of clocking structure has grown substantially in order to support high frequency clock domains. Modern clocking design needs to balance high frequency clocks with power, DFT, noise, circuit and physical design constraints.
Job duties and responsibilities:
- Design new clocks modules in order to support high frequency clock with all the above constraints.
- Architect and Implement the solutions to meet Security and Safety requirements for SOC Clocking.
- Come up with topologies to optimize the clock path for high-speed logic while meeting the functional and test requirements.
- Ability to come up with scalable flows to implement clocking for ever-increasing clock domains in our SOC architecture.
- Ability to design novel techniques to distribute clocks over long distances with low insertion delay, skew and OCV effects.
- Experience in RTL design (Verilog), verification and synthesis
- Strong coding skills in Perl or other industry-standard scripting languages
- Ability to interface with many groups
- Understanding of sub-micron silicon issues like noise, cross-talk, and OCV effects is a plus
- Prior experience in implementing on-chip clocking networks is a plus
Qualification & experience required:
B.Tech or M.Tech in EE, with a minimum of 2 years of relevant industry work experience.
For more than two decades, NVIDIA has pioneered visual computing, the art and science of computer graphics.
With a singular focus on this field, we offer specialized platforms for the gaming, professional visualization, data center and automotive markets.
Our work is at the center of the most consequential mega-trends in technology — virtual reality, artificial intelligence and self-driving cars.
Job/Req. ID: JR1931460
Location: Bangalore, KA
Job Category: Electronics Engineering
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Date of Publish: 29 June 2020