Synopsys India is conducting an internship for Engineers.
Job duties and responsibilities:
- The Intern(Technical) is responsible for a wide variety of verification tasks, including designing self-checking test benches using modern verification techniques;
- Designing verification components such as bus functional models, monitors, and behavioral models;
- Implementing functional coverage and assertions using System Verilog/C++;
- And developing test and functional coverage plans based on device specifications.
- This position will also be responsible for analyzing and debugging simulation failures, as well as analyzing functional coverage results.
- Strong Verilog coding skills
- Strong debugging skills
- Strong C/C++ or Perl or python scripting skills
- Knowledge on FPGA Architectures
- Highly skilled with one or more industry standard simulation tools Synopsys VCS, Verdi
- Strong understanding of typical design structures (FIFO’s, pipelines, memories, state machines, etc.)
- Fast leaner, comfortable and confident interacting with architects
- Excellent written and verbal communication skills
B.Tech/M.Tech in EE from a reputed institute
Job/Req. ID: 27717BR
Location: Noida, UP
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