Job description:
Faststream Technologies is conducting an interview for the post of Physical Design Engineer.
Job duties and responsibilities:
- Responsible for planning and execution of all aspects of Physical Design including Synthesis, Floor planning, Place and Route, Clock Tree Synthesis, Clock Distribution, IP integration, Extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out.
- Role involves analyzing DRC, LVS,ERC rule files for industry standard layout verification.
- Work experience in any of PCIe, MIPI, DDRs is preferable.
- Multiple Power Domain Analysis using standard Power Formats UPF/CPF.
Skills required:
- Experience in ASIC Physical Design RTL to GDSII Implementation flow.
- Experience with Logic synthesis, floor planning, power planning, placement, CTS, routing, timing sign-off, fill, etc.
- Experience with Low power design closure (UPF based implementation) and associated sign-off (SG-LP/VCLP/Conformal).
- Knowledge of Timing .lib generation, Physical View Generation (LEF, GDS, CEL, FRAM, NDM, etc.).
- Physical Verification (DRC/LVS/Density/Antenna etc.).
- Reliability Verification (EM/IR drop etc.).
- Well versed with TCL/Perl/Shell Scripting.
- EDA tool knowledge: Design Compiler, ICC/ICC2, Spectre, Virtuoso, Primetime, ICV.
- Responsible for planning and execution of all aspects of Physical Design including Synthesis, Place and Route, Clock Tree Synthesis, Clock Distribution, IP Integration, Extraction, Timing closure, Power and Signal Integrity Analysis, Physical Verification, DFM and Tape Out.
- Analyzing DRC, LVS, ERC rule files for industry standard layout verification.
- Multiple Power Domain Analysis using standard Power Formats UPF/CPF.
Qualifications and Experience required:
- BE/B.Tech/M.Tech in ECE/VLSI Design
- Experience: 1-5 Years in Physical Design
Job/Req. ID: N/A
Company: Faststream Technologies
Location: Bangalore, KA
Job Category: Electronics or VLSI Engineering
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