Synopsys India is conducting an interview for the post of ASIC Digital Design Engineer. Selected candidate will be a part of highly motivated and challenging high speed PHY design team working on most latest technologies. Opportunity to work with different design and verification teams across globe
- Good electrical networks/CMOS design analysis for debugging analog design
Good Knowledge on Verilog , system Verilog, VMM/UVM methodologies.
- Ability to create and debug mixed signal testbenches as per the design requirements.
- Implementing mixed signal checkers and measurements for the verification of mixed signal design
- Good knowledge on scripting languages like perl, python.
- Right attitude for exploring the design verification environment and come up with solutions for improving the flow/methodologies
Qualification & Experience required:
1 to 3 year experience in analog and mixed signal verification
Job/Req. ID: 28504BR
Location: Hyderabad, Telangana