T&VS Limited is conducting an interview for the post of DFT Engineer.
Job duties and responsibilities:
- RTL (Verilog/VHDL/SV) for ASIC – IP development or SOC integration.
Synthesis using DC or genus
- Verilog based Testbench and testcase developments. (ncsim or modelsim)
Qualification and Experience required:
Any candidate has 3- 6 years on ASIC domain. (NO FPGA)
- Some VLSI course
- DFT (SCAN, ATPG, BSCAN, MBIST)
- Layout, Memory compiler design or automation
- Knowledge in Clue logic or IP’s for Automotive.
- STA using primetime
- Formal Verification with spyglass or conformal
Highly competitive to match experience and capability
Job/Req. ID: HWVIND280618_40
Company: T&VS Limited
Location: Noida, UP
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