Synopsys is conducting an internship for Engineers.
Job duties and responsibilities:
You will be responsible for a wide variety of verification tasks, including designing self-checking test benches using modern verification techniques; designing verification components such as bus functional models, monitors, and behavioral models; implementing functional coverage and assertions using System Verilog/C++; and developing test and functional coverage plans based on device specifications. This position will also be responsible for analyzing and debugging simulation failures, as well as analyzing functional coverage results.
Qualifications and Experience required:
- B.Tech/M.Tech in EE from a reputed institute
- Strong Verilog coding skills
- Strong debugging skills
- Strong C/C++ or Perl or python scripting skills
- Knowledge on FPGA Architectures
- Highly skilled with one or more industry standard simulation tools Synopsys VCS, Verdi
- Strong understanding of typical design structures (FIFO’s, pipelines, memories, state machines, etc.)
- Fast leaner, comfortable and confident interacting with architects
- Excellent written and verbal communication skills
Job/Req. ID: 28778BR