Job description:
Synopsys India is conducting an interview for the post of ASIC/Layout Design Engineer.
Job duties and responsibilities:
- High Speed DDR/LPDDR I/O Layout design including GPIO and Special IO’s.
- Work with DDR PHY team, package engineers and system engineers to meet design specs.
- Perform scheduling duties
- Work with local team to support critical layout and floorplanning requirements
- Coordination duties with other layout teams both in Bangalore to detail out layout activities and obtain layout deliverables.
- Strict flow adherence and policing of internal policies to secure schedules.
Qualifications and Experience required:
Education: BTech/MTech in Electronics/Electrical engineering
Experience Required: 2 to 4 years
Skills/Experience required:
- Experience in Analog Mixed-signal layout and verification of high-speed digital and/or DDR IOs, Critical signal inclusion.
- Understanding of CMOS and FinFET layouts and process technology in 28nm and smaller.
- Good understanding of basic ESD and latchup layout design considerations.
- Familiarity with ASIC physical design flow: LEF generation, Place & Route & understanding of top level verification flow, DRC/LVS, LPE.
- Good understanding of IO frame and pitch requirements, power rail routings, IO abutment rules and requirements, bondpad layout, EM and IR considerations, DFM, etc.
- Scripting skills for layout automation is a plus.
- Good written and verbal communication skills in interactions with customers, and internal development teams.
- Understanding of Deep submicron effects and mitigation, Advanced tool usage, Advanced floorplanning techniques, understand digital flow, Advanced strategies.
Job/Req. ID: 28195BR
Company: Synopsys
Location: Bangalore, KA
Job Category: Electronics or Electrical or VLSI Engineering
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