Intel is conducting an interview for the post of CAD PDK Runset Development Engineer.
Job duties and responsibilities:
- In this job he/she will be involved in backend design verification code.
- DRC like runsets generation and debugging
- Key Aspects will be Layout tools Virtuoso Calibre, DRV IC Work Bench
- Runset Development Calibre PVS ICV Scripting Perl Python or TCL
- The candidate needs to have a minimum of 1 years of experience in the VLSI back end domain.
- He/she needs to have hands on experience on Layout editing tools
- CAD scripting languages like Python, Perl, TCL and knowledge of runsets will be an added qualification
- Candidate needs to have strong debugging skills and needs to be a team player demonstrating strong customer commitments
- BS or MS in Electrical/Electronics engineering 1 years of experience is required in the physical design verification is required
- Strong experience in developing the physical rule runsets in IC VCalibre is very much required
- Exposure to multi foundry technologies from TSMC Samsung Global and other competing foundries is very much desired
- Strong management experience in managing the developers QA engineers and other stakeholders is expected
- Intel technology exposure from the past experience will be a real plus
Job/Req. ID: JR0170935
Location: Bangalore, KA
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