Google is conducting an interview for the post of FrontEnd CAD Engineer.
About the job:
Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.
Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.
- Design, develop and deploy new RTL and/or DV flows, tools and features.
- Support (improve through profiling) execution of the tools and flows currently used in the RTL and/or DV design process.
- Design, develop, and support design methodologies, automation scripts, and write documentation.
- Be able to quickly ramp up on an existing front end methodology and support multiple projects.
- Bachelor’s degree in Electrical Engineering, Computer Engineering or Computer Science or equivalent practical experience.
- Experience in developing, supporting and debugging RTL tools and flows.
- Experience with developing and supporting RTL build and compilation flows, RTL connectivity flows, and IP to ASIC handoff/release flows.
- Experience in developing and supporting Design Data Management solutions (git/perforce), and continuous integration flows (Jenkins).
- Experience and understanding of multiple EDA design tools: VCS, Verdi, Spyglass, Coretools/Magillem, Cadence Xcelium.
- Exposure to front end design automation/CAD flows, including RTL lint, clock domain crossing, IP Release flow.
- Basic understanding of Verilog/System-Verilog RTL.
- Excellent scripting skills in Perl and/or Python, Makefile, Shell.
Job/Req. ID: N/A
Location: Bangalore, KA
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