GLOBALFOUNDRIES is conducting an internship for Engineers.
- The Physical Design engineer will be responsible for doing physical design implementation, timing closure, and Physical verification at the block and full chip level. Execute block-level and full chip floor planning, PG Planning, partitioning, placement, scan-chain-reordering, clock tree synthesis, timing optimization, SI aware routing, timing analysis/closure and ECO tasks (timing and functional ECOs), SI closure, design rule checks (DRC), and Logical vs. Schematic (LVS) checks, Antenna checks.
- Need good understanding in full chip physical design such as integration of blocks, top level floor planning, clock tree synthesis, timing constraints development and convergence. I/O placement and constraints.
- Understanding with UPF coding and modification as per design requirements is additional advantage.
- Need to take care of all aspects of physical design including synthesis, floor planning, place and route, Clock Tree Synthesis, Clock Distribution, extraction, Timing closure, Power and
- Signal Integrity Analysis, Physical Verification, DFM and Tape Out.
- Should be able to interface with the Front End Design team to resolve Design Issues Must possess hands on experience in P&R; from RTL to GDS including timing closure and Physical verification.
- Knowledge in Tcl/ Tk, PERL, Makefile is a Plus Excellent verbal and written communication skill is advantageous. Excellent interpersonal and analytical skills with an ability to work independently and within a team are required. Highly motivated, excellent team player, and customer oriented.
Bachelor or Master’s degree in Electrical and Electronics engineering.
Job/Req. ID: 21006138