AMD is conducting an interview for the post of Design Verification Engineer.
Job duties and responsibilities:
Candidate should have worked on complex design with hands on experience in developing testbench, UVC, test-planning and execute test plan, coverage development and closure. Candidate actively involve in technical discussion and test plan review.
Work with all stakeholders such as design architect and block designer to understand features to be verified. Follow the process and good practices to develop UVC and testbench for design verification.
Qualifications and other requirements:
- B.E/B.Tech in ECE, Electrical engineering degree or Master’s degree preferred with emphasis in Electrical/Electronics Engineering. Preferred VLSI major in post-graduation
- Experience requires demonstrated technical expertise in functional verification of complex designs including: test planning, test bench development, stimulus generation, checking, and functional coverage.
- Experience or exposure to Verilog, System Verilog, Object Oriented Programming/C++, Perl, and logic simulation is a requirement
- Experience or exposure to UVM/OVM is a must.
- Must demonstrate strong Object Oriented programing skills and concepts.
- Experience with memory controllers, dfi, dram memory models(ddr4/5, lpddr4/5, hbm, NVDIMM) and/or ddr phys is a plus
- Requires strong communication skills and the ability to work independently as well as in a cross-site team environment.
- Experience with memory controllers, dfi, dram memory models(ddr4/5, lpddr4/5, hbm, NVDIMM) and/or ddr phys is added advantage
- ASIC design verification experience with 3 to 10 years
- Hands on experience in developing complex UVC
- Good debugging skill and good knowledge of verification tool and methodology
- Hands on experience with coverage planning, coding, and coverage closure
- Should have worked on developing testplan at module level/IP level /Chip-level project
Job/Req. ID: 107502
Location: Bangalore, KA