Synopsys is conducting an interview for the post of R&D Engineer.
Jo duties and responsibilities:
- Responsible for designing, developing, troubleshooting, or debugging software programs.
- Design and Development of state of the art EDA software tools.
- Responsible for hardware compatibility and/or influences hardware design.
- Responsible for designing, developing, troubleshooting, or debugging software programs for our next generation Static Design Verification tool from Synopsys.
- Responsible for creating Verilog and VHDL unit test cases to validate the developed feature.
- Will be working closely with other teams both locally and globally.
- Developing new and innovative algorithms in the area of electronic design automation.
- Typically requires a minimum of 2 years of related experience.
- Works on collaborative or task-oriented projects.
- Resolves issues in creative ways.
- Ability to set and achieve goal in dynamic environment.
- Executes projects from start to completion.
- Contributes to moderately complex aspects of a project.
- One who believes in quality and wants to make a difference.
- Keen guide of more junior peers with aspects of their job.
- Networks with senior internal and external personnel in own area of expertise.
B.E / B.Tech / M. Tech. in Computer Science/Electrical/Electronics Engineering from reputed Universities
- Familiarity with ASIC design flow and the EDA tools and methodologies used therein.
- Fluent in C/C++ on Unix/Linux platforms.
- Possesses a solid understanding of algorithms and data structures.
- Good understanding of Verilog, SystemVerilog & VHDL HDL is desirable.
- Good understanding of basic scripting on Unix – bash/Perl/Python/Tcl will be an advantage.
- Experience in multi-threaded and distributed programming will be an advantage.
- Has exceptional desires to learn and explore new technologies
- Demonstrates good analysis and problem-solving skills.
Job/Req. ID: 32771BR