Synopsys is hiring VLSI Engineers for an internship.
Qualifications and other requirements:
- Must have BSEE, MSEE, or equivalent required with <1 years of experience
- Minimum 7.0 CGPA/ 70% in Bachelor’s in Engineering and 7.5 CGPA in Master’s till the current semester.
- Need to be backed with consistently high academics in 10th std and 12th standard.
- Strong fundamentals in Digital electronics. HDL Languages coding experience preferably in Verilog/VHDL/System Verilog
- Some knowlege in Formal verification, Simulation, writing of system verilog assertions, constraints properties
- Based on project assigned, the job would involve one or more of the following activities: Verilog/System Verilog/ VHDL coding,
- Working with EDA tools like VC Formal /VCS/SpyGlass , Writes testplans/ creates testcases/ setup benchmark designs to validate complex tool features,
- Diagnosis, troubleshooting and testing of frond end eda tools, Reviewing, resolving and maintenance of daily regressions & benchmark failures
Job/Req. ID: 31582BR