Synopsys is conducting an internship for Engineers.
- DDR I/O Circuit and layout design
Qualifications and other requirements:
- BE in EE/EC /MTech in VLSI
- Knowledge of CMOS processes and issues in deep submicron process technologies.
- CMOS circuit design and layout methodology & flow; basic understanding of analog/mixed signal circuitry, familiarity with basic ESD concepts is an advantage.
- Familiarity with ASIC design flow.
- Knowledge of JEDEC requirements for DDR interfaces & standards, DDR Timing, ODT and SDRAM functionality would be a plus.
- Ability to execute assigned circuit design tasks with best product quality and efficiency.
- Good written and verbal communication skills in interactions with internal development teams.
Job/Req. ID: 33670BR
Location: Bangalore, KA
Job Category: VLSI Engineering
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