SoC Design Engineering – DFT (JR0196891) | Intel | Bangalore, KA


Job description:

Intel is conducting an interview for the post of SoC Design Engineer.

Responsibilities and requirements:

  • Strong knowledge of DFT architectures and methodologies which includes Scan, ATPG, Mbist, BScan, IO DFx, analog DFT, JTAG, Boundary scan etc and proven knowledge of Verilog and System Verilog, RTL design and micro-architecture skills.
  • Strong knowledge of SoC tools/methodology ( VCS, Synthesis, Spyglass, Tessent Industry standard ATPG/MBIST tools design compiler etc. and also DFT design on Physical design highly desirable).
  • In addition, this position requires interaction and fulfilling the requirements of Intels post-silicon/ATE teams, Silicon Debug and understanding HVM (High Volume Manufacturing) requirements.
  • Strong debug skills and demonstrated experiences in Perl and TCL scripting are a must.
  • Strong Communications skills and the ability to effectively work with cross functional teams across geographies are required.
  • Intel is looking for smart and enthusiastic Engineers to develop Design For Testability for our SOCs.

Job/Req. ID: JR0196891

Company: Intel

Location: Bangalore, KA

Job Category: VLSI Engineering

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