Seagate is conducting an interview for the post of Physical Design Engineer.
About our group:
The group is responsible for development of full custom ASICs for leading edge storage solutions.
Job duties and responsibilities:
- Be able to work on block level Physical Design implementation using EDA tools for floor-planning, placement, and timing analysis.
- Understand semicustom IC design flow using IP libraries, concepts of Verilog netlist, meaning of timing constraints and QOR checks.
- Work on Physical design tasks including floor-planning, placement, clock tree synthesis, routing, timing analysis and equivalence checking for designs.
- Work on Timing analysis for sign-off corners and modes, report generation, analysis of the reports and suggesting timing/DRC fixes to fix the violations.
- Complete internship project as per plan.
Qualifications and skills required:
- Should be at least BE (ME/MTech preferred).
- Knowledge of ASIC design flow and tools
- Good understanding of Circuit design (Digital/Analog) and Logic design concepts.
- Good understanding of timing concepts like setup/hold time requirements, calculations of maximum frequency of circuit operations, effect of transition and load on circuit performance and power.
- Basic understanding of CMOS fabrication process.
- Basic understanding of layout design for CMOS and BJTs.
- Basic understanding of power dissipation in different types of circuits.
- Strong analytical, problem solving and debugging skills.
- Good team player with strong verbal and written communication skills.
- Self-motivated and ability to quickly learn new tools and technologies.
- ASIC design flow, basic EDA tools for Physical design implementation.
- Place and Route, Timing Analysis, Equivalence check.
- Perl, Tcl, Shell or other scripting languages.
Job/Req. ID: 823667500
Location: Pune, MH
Job Category: VLSI Engineering
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