Job description:
Cadence is conducting an interview for the post of Design Engineer II.
Job requirements:
- Knowledge on ASIC/IP/Subsystem/SOC Verification primarily in PCIe / NVMe
- Worked on Verification environment and methodologies using Verilog / System Verilog / UVM / OVM / “e” Specman based languages
- Knowledgeable in Cadence VIPs, Verilog Real modelling of analog behavior and debug in various Industry Simulation tools
- Regression setup Coverage / Metric analysis and Vplan setup are preferable.
- BTech/MTech
Job/Req. ID: R36818
Company: Cadence
Location: Bengaluru, KA
Job Category: VLSI Engineering
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