Design Verification Engineer | Synergic Emergence | Bengaluru, KA

Job description:

Synergic Emergence is conducting an interview for the post of Design Verification Engineer.

Job duties and responsibilities:

  • Debug skills, Debugging RTL in block and/or chip-level, IP block interoperability and SOC/System level, System Verilog,
  • UVM, and scripting languages like Python and Tcl. Full Chip Verification. Writing System Verilog Assertions (SVAs).
  • HW/SW Co-Verification, NC Verilog, VCS, QuestaSim, Execute Chip-Level Verification Plans

Job/Req. ID: N/A

Company: Synergic Emergence

Location: Bengaluru, KA

Job Category: VLSI Engineering

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