Job description:
Micron Technology is hiring engineers for various job openings.
| Job/Req. ID | Job Title | Skills required | Experience |
| J181173 | Solution Architect | Big Data, Hive, Spark, Hadoop, Apache Spark, AWS/ Azure/ GCP | 9 – 18 Years SMAI |
| JR8706 | Principal Hardware Engineer, CSSD | Hardware Board Design, Storage experience, architecture, PCIe, DDR 1 | 0-17 Years CSSD |
| JR4268 | Principal Engineer – SSD Validation – Hyderabad | Validation , Python Scripting , Embedded systems , Firmware | 10-15 Years CSSD |
| JR7602 | Principal Engineer – SSD PDL System Engineering | Product Development Leadership ,FW Understanding | 10-15 Years CSSD |
| JR15923 | SSD Validation Principal Engineer – Bangalore | Validation , Python Scripting , Embedded systems , Firmware 10 | 15 Years CSSD |
| JR17565 | Staff Engineer ESSD Firmware | SSD firmware, NVMe, firmware Dev, Python ,FTL 4-12 Years ESSD | 4-12 Years ESSD |
| JR16843 | Engineering Director | Architecture PCIe, NVMe, ZNS, NAND media management and algorithm, Firmware, SSD FTL, Architect | 15-20 Years ESSD |
| JR17771 | Staff Engineer – ESSD Firmware | SSD Firmware Dev, FTL, SATA/SAS/ NVMe | 5-15 Years ESSD |
| JR17077 | Principal Engineer I | SSD Software C, C++ and Python, debug interface protocols (SATA, SAS, NVMe),Design and develop | 10-17 Years ESSD |
| JR18204 | Staff Engineer – ESSD Firmware | SSD Firmware Dev ,FTL, SATA/SAS/ NVMe | 5-12 Years ESSD |
| JR17544 | Principal Engineer , ASIC Layout | Analog Layout ,Serdes, DRC/LVS, latest technology nodes (12nm and below). | 8-17 Years ASIC |
| JR19090 | DEG Design Director | CMOS Circuit Design, Analog Design, Layout and Device Physics | 15-23 Years DEG Design |
| JR19092 | Senior Manager, DEG India Operations | Develop and drive engagement, recognition, and cost management strategies, establish relationships and act as liaison between organizations, Drive special projects | 15-20 Years DEG Design |
| JR19696 | Senior Manager – IP Circuit Group | leading big circuit design, verification and layout team. Circuit verification and optimization including layout verification and parasitic extractions of the circuits | 15-20 Years DEG Design |
| JR20041 | DEG IP Circuit Design Director | leading big circuit design, verification and layout team. Circuit verification and optimization including layout verification and parasitic extractions of the circuits | 15-23 Years DEG Design |
| JR8100 | Director, MDSI India | Signal Integrity , Power Integrity, Hspice, Board Design, Hardware Design | 18-25 Years DEG Design |
| JR5545 | Senior/Staff/Principal Engineer, Memory Design | CMOS Circuit Design, Finesim and/or Hspice, Verilog modeling, OTP, IO Design | 7-18 Years DEG Design |
| JR12142 | SENIOR MANAGER DEG DESIGN | AMS Verification, Co-sim, PLI coding, SV UVM, DDR or memory | 15-20 Years DEG Design |
| JR12145 | Manager Memory Circuit Design Verification | AMS Verification, Co-sim, PLI coding, SV UVM, DDR or memory | 12-16 Years DEG Design |
| JR9855 | Senior Manager/ Manager – Memory Circuit Design Verification | AMS Verification, Co-sim, PLI coding, SV UVM, DDR or memory | 10-18 Years DEG Design |
| JR9856 | Senior/Staff/ Principal Engineer – Memory Circuit Design Verification | AMS Verification, Co-sim, PLI coding, SV UVM, DDR or memory | 5-15 Years DEG Design |
| JR9857 | Senior/Staff/Principal Engineer- Design Verification | SV UVM, DDR/ Memory, Digital or Circuit | 5-15 Years DEG Design |
| JR 8395 | Senior/Staff Engineer Analog Design | Analog Design, Circuit design, PLL, Timing DDR or memory | 4-15 Years DEG Design |
| JR8081 | Staff/Principal – Signal Integrity | SI/PI, EMI theory, Simulation, HFSS, ADS, Analog design | 8-15 Years DEG |
| JR13297 | *Manager – Layout* | Analog Layout, DRC, CVS, Virtuoso, Mentor Graphics | 12-16 Years DEG Layout |
| JR13303 | Senior Manager – DEG Layout | Analog Layout, DRC, CVS, Virtuoso, Mentor Graphics | 15-20 Years DEG Layout |
| JR9400 / JR13302 | Senior/Staff/Principal – Analog/Memory Layout Analog Layout | DRC, CVS, Virtuoso, Mentor Graphics | 5-15 Years DEG Layout |
| JR235082 | Principal Engineer II – Design Tech Lead | Nand flash , Digital/Mixed/Analog circuits , Full chip integration | 10-15 Years NVE Design |
| JR7341 | Staff AMS Core Design Engineer | NVM , AMS Design , Analog and mixed Signal , Simulations , Scripting | 8-12 Years NVE Design |
Company: Micron Technology
Location: Hyderabad, Telangana
Job Category: VLSI Engineering
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Interested candidates can send their resume to [email protected]
