Job description:
Cadence is looking for a talented individual to work in the DEG (Design Enablement Group) team of the Cadence Tensilica IP.
Tensilica has unique technology to build configurable and extensible processor IP. In this team we develop methodology and implementation flows that can achieve the best possible PPA (Performance, Power and Area) for these processor IP.
Job duties and responsibilities:
- Develop and maintain flows and scripts for the physical implementation.
- Debug and optimize the flow for performance-oriented and power-oriented IP cores in advanced process nodes, such as 16nm/7nm/5nm.
- Manage the regression infrastructure that tracks the quality of the RTL/flow development as well as the PPA of the key designs.
- Participate in benchmarking PPAs for customer engagements.
Qualifications and Experience required:
- MS in Electrical Engineering or Computer Science
- Strong understanding of digital logic design, processor design, and computer architecture is desirable.
- Must have excellent knowledge of ASIC design flows and issues. Prior working experience on any Cadence physical implementation tool is a plus.
- A good working knowledge on Perl is required. Experience on any other programming language is a plus.
- Must be an excellent team player in a fast-paced environment.
Job/Req. ID: R37950
Company: Cadence
Location: San Jose, Pune, Noida, Bangalore, Cary, Cork, 01Austin
Job Category: Computer Science or Electrical or VLSI
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