Job description:
Synopsys is conducting an interview for the post of ASIC Digital Design Engineer.
Job duties and responsibilities:
The Digital Design Verification Engineer works on PHY IP verification related to complex protocols. The position offers excellent learning and growth opportunities. This is a technical individual contributor role offering a challenging career path.
The role involves developing and working on verification of high speed PHYs and Serdes. Additionally you will be involved in:
- Verification plan development and its review
- Verification environment development
- Debug of simulations, including those of real signals modeled using SV for analog
- RTL, GLS, Co-simulations, FW simulation & coverage closure
- Deliver high quality RTL and other simulation models to customer
- Participate in technical reviews and contribute actively
- Participate in customer support with bring-up of IP in customer simulation environment
- Participate in review of SERDES / PHY / Controller IP specification to validate compliance to protocol of interest
- Follow and improve development process ensuring high quality output.
Qualifications and experience required:
Candidate should be B.E./B.Tech or M.E./M.Tech in Electronics / Telecommunication / Computers as major subjects.
Skill set required:
- Basic knowledge of HVL, or HDL like VHDL, System Verilog
- Knowledge of Perl/Shell scripts
- Knowledge of protocols like Ethernet, PCIe, other networking protocols
- In addition the candidate should have good communication skills, be a team player with good problem solving and interpersonal skills.
Job/Req. ID: 40701BR
Company: Synopsys
Location: Bangalore, KA
Job Category: VLSI or Electronics or Telecom or Computer Engineering
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