Job description:
Intel is conducting an interview for the post of Layout Design Engineer.
Requirements:
- Strong VLSI design knowledge, Custom/Analog Layout design and scripting.
- Experience in Memory layout design, Custom , ASIC Physical DesignElectronic Design Automation tools, flows and methodology: Virtuoso XL, Layout cleanup expertise DRCs, density, ipc, etc.
- Circuit design knowledge, TCL, Perl and/or C++ programming
- Strong analytical ability, problem solving and communication skills
- Ability to work independently and at various levels of abstraction
- Work experience with external and/or internal key stake holders spread across multiple geography
Qualifications required:
BE/ BTech in Electronics And communication
Inside this business group:
In the Design Engineering Group (DEG), we take pride in developing the best-in-class SOCs, Cores, and IPs that power Intel’s products. From development, to integration, validation, and manufacturing readiness, our mission is to deliver leadership products through the pursuit of Moore’s Law and groundbreaking innovations. DEG is Intel’s engineering group, supplying silicon to business units as well as other engineering teams. As a critical provider of all Intel products, DEG leadership has a responsibility to ensure the delivery of these products in a cost efficient and effective manner.
Job/Req. ID: JR0238727
Company: Intel
Location: Bangalore, KA
Job Category: Electronics or VLSI Engineering
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