NVIDIA is seeking a passionate, creative, and highly motivated engineer to work on architectural power estimation for the world’s leading GPUs and SOCs.
Job duties and responsibilities:
In this position, the responsibility includes development of advanced power models to estimate chip and board power under product driven use cases. You are expected to understand the high-level chip architecture, application use-cases, low power design techniques, process technology aspects which impact dynamic and leakage power, develop the estimation infrastructure, estimate power consumption under various scenarios. You will be working with architecture, design, synthesis, timing, circuit, and post silicon teams to accomplish your tasks.
This position offers the opportunity to have real impact in a dynamic, technology-focused company impacting product lines ranging from consumer graphics to self-driving cars and the growing field of artificial intelligence. We have crafted a team of outstanding people stretching around the globe, whose mission is to push the frontiers of what is possible today and define the platform for the future of computing. At NVIDIA, our employees are passionate about parallel and visual computing. We’re united in our quest to transform the way graphics are used to solve some of the most complex problems in computer science.
- Architecture, development and correlation of power estimation models/tools for NVIDIA’s chips.
- Help architect and develop power models for use-cases, Idle power and IO power.
- Chip in to design the tools based on these models and their testing methodology/infrastructures.
- Correlate and Calibrate the power models using measured silicon data.
- Analyze and help decide the chip configuration and process technology options to optimize power/performance for NVIDIA’s upcoming chips.
- Help study and contribute to Performance/Watt improvement ideas for NVIDIA’s GPUs and SOCs.
Qualifications and experience required:
- B.Tech./M.Tech and 1+ years of experience related to Power / Performance estimation and optimization techniques.
- Strong fundamentals in power including transistor-level leakage/dynamic characteristics of VLSI circuits.
- Familiarity with low power design techniques such as multi VT, Clock gating, Power gating, and Dynamic Voltage-Frequency Scaling (DVFS).
- Strong background in power estimation techniques, flows and algorithms.
- Good programming skills – Python preferred. Good skills with object-oriented programming and design.
Ways to stand out from the crowd:
- Exposure to lab setup including power measurement equipment such as scope/DAQ with ability to analyze board level power issues is a plus.
- Exposure to power analysis EDA tools such as PTPX/EPS.
- Good communication skills & desire to work as a great teammate.
Job/Req. ID: JR1965613
Location: Bangalore, KA
Job Category: VLSI Engineering
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