ASIC Physical Design Engineer, Intern (44541BR) | Synopsys | Hyderabad, Telangana

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Job description:

Synopsys is conducting an internship for Physical Design Engineers.

About the group:

The broad DesignWare IP portfolio includes logic libraries, embedded memories, embedded test, analog IP, interface IP, security IP, embedded processors, and subsystems. To accelerate prototyping, software development and integration of IP into SoCs, Synopsys’ IP Accelerated initiative offers IP Prototyping Kits and IP subsystems. Our extensive investment in IP quality, comprehensive technical support and robust IP development methodology enables designers to reduce integration risk and accelerate time-to-market.

This internship will be with Synopsys’s Solutions IP group in Hyderabad.

Job duties and responsibilities:

  • As an intern, you will be involved in Block level Physical Design implementation of High-speed designs from RTL to GDS for latest technology nodes. The work involves design and automation of strategies/techniques to improve timing and power. Generation of timing clean and power efficient layout from RTL using EDA tools and Place and Route flows, which involves running synthesis, floor-planning, placement, cts, routing, static timing analysis and physical verification.
  • Prior Design experience is not a must for this position, however having experience would be beneficial. Post Graduate students are highly encouraged to apply.

Minimum skill requirements:

  • Understanding of Digital Place and Route flow from RTL to GDS and basic knowledge of various steps involved in it like Synthesis, Placement, CTS, LVS and DRC etc.
  • Basic Knowledge of static timing Analysis and understanding of setup and hold checks.
  • Basic knowledge of Power Dissipation in CMOS VLSI circuits.
  • Basic Digital design concepts and understanding of HDL languages VHDL/Verilog.
  • Basic experience with programming in C/C++ or Perl/TCL.
  • Basic Knowledge of analog circuit design concepts and spice simulation are a plus.

Qualifications required:

  • Master’s or PhD’s degree in VLSI engineering or similar technical field.
  • Basic Digital design and VHDL or Verilog language concepts.
  • Basic exposure to EDA tools for Place and Route Implementation and layout verification.
  • Basic programming skills in languages such as C or Perl/TCL
  • Ability to provide automation​ for rapid and dynamic design needs is highly sought-after.

Job/Req. ID: 44541BR

Company: Synopsys

Location: Hyderabad, Telangana

Job CategoryVLSI Engineering

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