Job description:
Cadence is conducting an interview for the post of Principal RTL Design Engineer.
Job duties and responsibilities:
- Design & synthesize for a complex SerDes IPs in various technology nodes (> 100G rates)
- Work with Analog design teams to co-develop algorithms, feedback design loops as well as high speed critical digital circuits
- Good understanding of working with signal processing IPs in terms of knowing calibrations, PLLs, dividers, FIFO design and reset distribution
- Proficient in RTL coding, DSP datapath designs as well as control FSM ensuring timing closures at 2GHz and above at lower geometry nodes
- Very good in understanding and defining timing constraints and critical high speed path timing closure working with BE teams
- General flow understanding of various stages and steps involved in Serdes design flow will be a huge plus including AMS modelling and SV RNM verification.
- Good knowledge of functional (analog BIST, eye-surf) and structural DFT (Bscan, Scan etc..) for high speed PHY IPs will be a plus.
- Work closely with analog and validation teams to bring up silicon and fine tune and debug performance issues at high speed
- Strong knowledge on complete Implementation flows and rigorous checks before delivery to other teams or customers ex- LINT, SDC, CDC, DFT, Low power and trial PnR
Job/Req. ID: R43498
Company: Cadence
Location: Bangalore, KA
Job Category: VLSI Engineering
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