ASIC RTL Integration Engineer | Google | Bangalore, KA

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Job description:

Google is hiring for the post of ASIC RTL Integration Engineer.

About the job:

Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.

With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.

Google’s mission is to organize the world’s information and make it universally accessible and useful. Our Devices & Services team combines the best of Google AI, Software, and Hardware to create radically helpful experiences for users. We research, design, and develop new technologies and hardware to make our user’s interaction with computing faster, seamless, and more powerful. Whether finding new ways to capture and sense the world around us, advancing form factors, or improving interaction methods, the Devices & Services team is making people’s lives better through technology.

Job duties and responsibilities:

  • Manage activities such as plan tasks, hold code and design reviews, contribute to sub-system/chip-level integration.
  • Interact closely with architecture team and develop implementation strategies to meet quality, schedule, and power performance area for sub-system/chip-level integration.
  • Interact closely with subsystem team and plan SoC milestones, plan quality checks as part of SoC milestones and guide subsystem teams with SoC level requirements (e.g., IPXACT, CSR, Lint, CDC, SDC, UPF, etc.).
  • Work closely with the cross-functional team of Verification, Design for Test, Physical Design,
  • Emulation, and Software teams to make design decisions and represent project status throughout the development process.

Minimum qualifications:

  • Bachelor’s degree in Electrical Engineering or equivalent practical experience.
  • Experience in design and multi-power domains with clocking.
  • Experience in coding using Verilog or System Verilog.

Preferred qualifications:

  • Master’s degree in Electrical Engineering, or a related field.
  • Knowledge of one or more of the following: Process Cores, Interconnects, Debug and Trace, Security, Interrupts, Clocks/Reset, Power/Voltage Domains, PinMux.
  • Understanding of cross-domain involving domain validation, design for testing, physical design, and software.

Job/Req. ID: N/A

Company: Google

Location: Bangalore, KA

Job CategoryVLSI Engineering

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