Synopsys is conducting an interview for the post of Verification IP Engineer.
Job duties and responsibilities:
- The candidate would be part of the VIP group responsible for development of Verification IPs.
- Core responsibilities would include Designing and developing the VIP/Test-bench, Creating Verification plans, Coding sequences/Test-scenarios, Coverage driven verification.
- The responsibility would also include enhancement of the existing Verification IP products and interface with customers during VIP deployment.
- Bachelors/Masters with good academic record.
- Hands-on experience in developing HVL based verification environments, preferably using System Verilog.
- Exposure to coverage driven verification.
- Demonstrates good analysis and problem-solving skills.
- Have a strong passion for work and driving things to closure.
Job/Req. ID: 44699BR
Location: Noida, UP
Job Category: VLSI Engineering
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