Google is conducting an interview for the post of RTL Design Engineer.
About the job:
Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
As a key member of the team, you manage projects in multiple areas with your expertise. You also monitor the performance of vendors working on projects and evaluate new technologies.
Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.
Job duties and responsibilities:
- Perform Verilog/SystemVerilog RTL coding, function/performance simulation debug and Lint/CDC/FV/UPF checks.
- Develop Register Transfer Level (RTL) implementations that meet competitive power, performance and area targets.
- Participate in synthesis, timing/power closure and Field-Programmable Gate Array (FPGA)/silicon bring-up.
- Create tools/scripts to automate tasks and track progress.
- Work with multi-disciplined and multi-site teams in RTL design, verification, or architecture/micro-architecture planning.
- Bachelor’s degree in Electrical Engineering, Computer Science or equivalent practical experience.
- 1 year of experience in designing RTL digital logic using Verilog/SystemVerilog for Field-Programmable Gate Array (FPGA)/Application-Specific Integrated Circuits (ASICs).
- Master’s degree in Electrical Engineering or Computer Science, or a related field.
- 2 years of experience in designing RTL digital logic using Verilog/SystemVerilog for FPGA/ASICs.
- Experience implementing Camera ISP image processing blocks or other multimedia IPs such as display or video codec.
- Experience in area, power, and performance optimization.
- Proficient in scripting languages, C/C++ programming and software design skills.
Job/Req. ID: N/A
Location: Bangalore, KA
Job Category: VLSI Engineering
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