Job description:
Cadence is hiring a Design Engineer in Bangalore.
Job duties and responsibilities:
The responsibility entails performing pre silicon Physical Layer Electrical Validation infrastructure development as well as post silicon validation primarily on Cadence’s High Speed SERDES Test chips, ie, activities involving (but not limited to) designing the hardware and software architecture required to test the test chips (be it the test PCBs, controlling FPGA platforms, Labview/python automation for controlling the HW etc), defining test plans for rigorously testing the compliance of the Test chips to the Physical Layer Electrical specifications, implementing these tests as planned, generating high quality test reports based on the test results etc.
Qualifications and experience required:
- 0-2 years of experience in Post-Silicon Validation related or hardware analog system level circuit design related activities
- Candidates are certainly expected to be passionate about analog and digital electronic circuit design aspects as well as signal processing related aspects.
- Experience in using lab equipment such as Oscilloscopes, Network Analyzer, Bit Error Rate Tester (BERT) etc is a significant added plus.
- Familiarity with concepts of high speed serial communication – Transmission lines, clock and data recovery
- Familiarity with board schematic/layout design and lab bring-up is an added plus
- Familiarity with Verilog/VHDL RTL coding, RTL design for FPGA, Labview, python, C/C++, TCL is an added plus
- BE/BTech/MTech/M
Job/Req. ID: R43535
Company: Cadence
Location: Bangalore
Job Category: VLSI Engineering
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