Morris Mano’s Digital Design Reference to brush up the basics
Job description:
Google is conducting an interview for the post of Hardware Engineer.
About the job:
Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.
Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.
Job duties and responsibilities:
Work with the SoC Development teams to Verify/simulate/debug FUNC/HSIO blocks RTL/Gate level, ATE/Bench pattern generation with target coverage and Silicon Debug.
Be familiar with the SoC level DV/UVM environment, JTAG/APB/AHB/AXI based protocols and the requirements for verifying SubSystems on SOC level.
Minimum qualifications:
- Bachelor’s degree in Electrical Engineering or equivalent practical experience.
- 2 years of experience working in an SoC Chip level/Cluster/Sub-System Verification.
- Experience on ATE pattern generation/conversion, Virtual Tester simulation and Bench CSV generation.
Preferred qualifications:
- Experience with DV and Test case development for RTL verification, Gate Level (GLS) Verification, Timing (SDF) GLS and Power Aware (PAGLS) verification with Synopsys/Mentor or Cadence or equivalent tools.
- Experience in ARM Cores, GPU, DSP and/or HSIO PHY design verification, Test bench creation.
- Knowledge of HVL methodology (UVM/OVM/VMM) and HDL (System Verilog, Verilog).
- Familiarity with different test pattern formats such as STIL, WGL, SVF, VCD, eVCD and ATE fail datalogs.
- Ability to partner with ATE team on Silicon Debug and ensure the patterns stability across voltage/temperature/process corners.
Job/Req. ID: N/A
Company: Google
Location: Bangalore, KA
Job category: Electrical or VLSI Engineering
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