Job description:
Intel is hiring for the post of Layout Design Engineer.
Job duties and responsibilities:
- Creates mask layouts of integrated circuits for a given specification and runs complete set of design verification tools for process design rules, electron migration, voltage drop (IR), ESD, and other reliability checks on the layouts.
- Develops custom layout design memory compilers (e.g., bit cells, SRAMs, Register Files).
- Performs detailed physical array planning, area optimization, critical wire analysis, custom leaf cell layout.
- Provides feedback to circuit design engineers for new feature feasibility studies and implements circuit enhancement requests.
- Knowledge of and experience with advanced FinFET processes.
Qualifications and experience required:
- Minimum qualifications are required to be initially considered for this position.
- Preferred qualifications are in addition to the minimum requirements and are considered a plus factor in identifying top candidates.
Minimum qualifications:
1-3 years experience
Preferred qualifications:
Cadence Virtuoso Layout Editor tool knowledge is a plus.
Requirements listed would be obtained through a combination of industry relevant job experience, internship experiences and or schoolwork/classes/research.
Job/Req. ID: JR0252094
Company: Intel
Location: Bangalore, KA
Job Category: VLSI Engineering
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