Google India is conducting an interview for the post of Physical Design Engineer, CPU Subsystem.
Our computational challenges are so big, complex and unique we can’t just purchase off-the-shelf hardware, we’ve got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google’s services. As a Hardware Engineer, you design and build the systems that are the heart of the world’s largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.
With your technical expertise, you lead projects in multiple areas of expertise (i.e., engineering domains or systems) within a data center facility, including construction and equipment installation/troubleshooting/debugging with vendors.
Google’s mission is to organize the world’s information and make it universally accessible and useful. Our team combines the best of Google AI, Software, and Hardware to create radically helpful experiences. We research, design, and develop new technologies and hardware to make computing faster, seamless, and more powerful. We aim to make people’s lives better through technology.
Job duties and responsibilities
- Manage end-to-end ownership of one or more physical design partitions or top level including layout verification, EMIR and timing closure.
- Optimize and drive power, performance and area based on IP needs.
- Develop high performance hardware and software to enable Google’s continuous innovations in working with Application Specific Integrated Circuit (ASIC).
- Bachelor’s degree in Electrical Engineering or equivalent practical experience.
- 3 years of experience in high-performance, high-frequency designs.
- Master’s degree in Electrical Engineering, or a related field.
- 4 years of experience in physical design, including clock/voltage domain crossing, Design for Testing (DFT), timing analysis, EMIR and low power designs.
Job/Req. ID: N/A
Location: Bangalore, KA
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