Job description:
Broadcom’s Central Engineering Group (CEG) is looking for a professional to join our team as a modeling engineer for the development of functional, timing, power and DFT simulation models.
Job duties and responsibilities:
This role will focus on developing and debugging memory IP (SRAM, RF, CAM, ROM, etc.) EDA models used in ASIC-like design flows by chip teams throughout the company. This is a “learn through doing” position with the expectation that the candidate can pickup skills quickly, be proactive, analyze and discuss complex technical issues, is able to work collaboratively with team.
The candidate must possess excellent problem solving skills.
Essential responsibilities:
- Candidate will work on developing functional/timing/dft models for memory IP based on a design specification.
- Execute third party tools such as Synopsys and Mentor, to verify memory models accurately reflect silicon behavior.
- Continuously improve memory models and model generation flows for better performance, user experience, and quality.
- Work directly with IP design teams, compiler teams and tool vendors globally to help resolve model related issues, and find timely solutions.
- Integrate automation software into memory compilers to generate CAD models used in DFT/CAD tools used in ASIC development flows.
- Develop and debug software written primarily in Perl, with some Python.
- Respond to library support requests and address tickets on model issues from product teams across Broadcom.
Qualifications and experience required:
- Education and Experience target (flexible): Bachelors +2 , Masters degree in Electrical Engineering, Electronics Engineering, Computer Science, or related semiconductor curriculum.
- Have at least 2 years experience.
Job/Req. ID: R018775
Company: Boradcomm
Location: Bangalore, KA
Job Category: VLSI or Electronics or Electrical or Computer Science
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