Job description:
Intel is conducting an interview for the post of Physical Design Engineer.
Job duties and responsibilities:
Creates bottoms up elements of chip design including but not limited to:
- Device cell and block level layouts Block level floor plans abstract view generation
- RC extraction and schematic layout verification and debug using phases of physical design development including parasitic extraction clock generation custom polygon editing auto place and route algorithms floor planning full chip assembly RV DFM Density and verification
- Troubleshoots design issues and applies proactive intervention
- May schedule staffing execution and verification of complex chips development and execution of project methodologies and/or flow developments
Qualifications required:
- BE or BTech or equivalent technical degree in Electronics Electrical engineering
- Knowledge in Layout Designing
Experience/Skills/Additional qualifications include:
- Proficiency in multiple levels of layout design which includes data path register files and standard cell designs Proficiency in floor planning activities which include FUBunit level assembly routing and integration of custom blocks in to the FC floorplan
- Ability to comprehend issues of RC delay electromigration selfheating and cross capacitance
- Ability to recognize failure prone layout structures and proactively contact engineers for guidance and produce electrically robust layout
Job/Req. ID: JR0260285
Company: Intel
Location: Bangalore, KA
Job Category: VLSI or Electronics or Electrical Engineering
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