Analog Layout Design Engineer (JR0264513) | Intel Job | Bangalore, KA

Job description:

Intel is conducting an interview for the post of Analog Layout Design Engineer.

Job duties and responsibilities:

You will be designing the layout of sensitive analog components, although not limited to, such as receivers, transmitters, clocking, ADC/DAC PLL and LDO circuitry for High Speed IO’s, Ethernet and Foundational IP’s in Intel’s current and next-generation process nodes. Responsibilities of the role include, although not limited to:

  • Designs complex layouts of analog signal circuits for a given design specification and runs complete set of design verification tools for process design rules, electron migration, voltage drop (IR), ESD, and other reliability checks on the layouts.
  • Designs and analyzes floorplans, power grid, ESD, bumps, and performs all required verification on the analog blocks.
  • Performs the floor-planning and detailed signal planning of complex analog circuits to meet performance and electrical requirements (shielding, matching) for critical signals to optimize for area, power, RV, and performance.
  • Develops and drives new and innovative analog layout methodologies to improve layout productivity and quality.
  • Collaborates with analog circuit design, SD, SIPD, process technology, and package design teams to meet design specifications, plan work, and negotiate layout tradeoffs as needed.
  • Troubleshoots a wide variety of issues up to and including design and tool/flow/methodology used in analog layout design.
  • Excellent communication and expected to drive clarity across customers, stakeholders, partners, managers by clearly and concisely summarizing problems, status, data, and proposals both orally and in writing.
  • Excellent teamwork and being flexible in assignment as per project needs.

Qualifications and experience required:

M.Tech in Electronics/Electrical/VLSI Design Engineering with 1+ years or B.Tech Electronics/Electrical/VLSI Design Engineering with 2+ years of relevant experience in Analog and SERDES IO IP design e.g. GPIOs, Thermal Sensor, PLL, ADC/DAC/ Voltage regulators/LDOs, AIB, HBMIO, DDR, HDMI/DP IO, MIPI IO etc.

Preferred qualifications:

  • Analog Device and Metal Layout Fundamentals Analog/Mixed Signal Fundamentals Reliability Verification.
  • Cadence Virtuoso Layout Suite Full Chip Top Metal/Analog Routing Design IP Design Planning.

Job/Req. ID: JR0264513

Company: Intel

Location: Bangalore, KA

Job Category: Electrical or Electronics or VLSI Engineering

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