Job description:
Google is conducting an interview for the post of ASIC Design Verification Engineer.
Job duties and responsibilities:
- Plan the verification of IPs and Subsystem level by fully understanding the design specification and interacting with architecture and design engineers to identify important verification scenarios.
- Create and enhance constrained-random verification environments using System Verilog and Universal Verification Methodology (UVM).
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Identify verification holes and show progress towards tape-out.
Minimum qualifications:
- Bachelor’s degree in Electrical/Computer Science Engineering, or equivalent practical experience.
- Experience verifying digital systems with standard IP components/interconnects, including microprocessor cores and hierarchical memory subsystems.
- Experience in verifying digital logic at RTL using SystemVerilog for FPGAs and ASICs.
- Experience verifying digital IP and subsystems.
Preferred qualifications:
- Master’s degree in Electrical Engineering, Computer Science, or a related field.
- Experience creating/using verification components and environments in methodology.
- Experience with image processing, computer vision, and/or machine learning applications.
- Experience in prototyping and debugging systems on Field Programmable Gate Array (FPGA) platforms.
- Experience with performance verification of ASIC components.
- Familiarity with ASIC standard interfaces and memory system architecture.
Job/Req. ID: N/A
Company: Google
Location: Bangalore, KA
Job Category: Electrical or Computer Science or VLSI Engineering
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