Description:
Indian Institute of Technology, Patna is looking for a Junior Research Fellow.
Responsibilities:
Designing using Cadence and getting fabricated CMOS Phase-locked Loops with Ultra low Jitter, Low Spur and Low power consumption for High Speed Data Converters, Wi-Fi 7, 5G and beyond Communication Systems
Qualifications required:
- For candidates with M.Tech. / ME / MS degree in VLSI / Communication / Electronics / Instrumentation: first class (minimum 60% marks or 6.50 CPI) in M.Tech. / ME / MS with GATE / NET qualifications and first class (minimum 60% marks or 6.5 CPI) in B.Tech. / BE.
- For candidates with B. Tech. / BE in Electronics / Electrical / Instrumentation) as qualifying degree: 70% marks or 7.50 CPI in B.Tech./BE from institutes other than IITs/IISc and 7.0 CPI in B.Tech. from IITs and IISc.
- Candidate with knowledge of designing CMOS circuits, eps PLL, and experience of using CAD tools like Cadence will be given preference
The applicant should have qualified GATE or any other national level exam like NET
Fellowship:
₹ 37000/- for the first two years followed by ₹ 42,000/- for the 3rd year
Duration:
Initially for 1 year, extendable by two more years.
Job/Req. ID: N/A
Company: Indian Institute of Technology
Location: Patna, Bihar
Job Category: ECE or Instrumentation or VLSI Engineering
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