Job description:
Synopsys is conducting an interview for the post of ASIC Physical Design Engineer.
Job duties and responsibilities:
In this role, you will work on development of robust ASIC design flow to build & verify our standard cell libraries to achieve the best PPA with all aspects of quality. Work involves Place and Route using ICC/ICC-II/Fusion Compiler.
Qualifications and experience required:
- Bachelors or Masters degree in electronics or electrical engineering or equivalent from reputed universities with 2-3 year experience in ASIC design or internship of few months
- Working experience on advance technology nodes like 28nm,16nm,14nm,10nm, 7nm with different foundries
- Clear understanding of CMOS & ASIC flow in submicron process nodes
- Knowledge on Place & route , physical verification (DRC/LVS) & Timing analysis skills
- Be familiar with all stages in the ASIC design flow including Synthesis, DFT , timing analysis, floor planning, power planning, CTS, ECO flow, STA, power analysis
- Be familiar with the Low power concepts & UPF/CPF format
- Good understanding about Tech file, liberty, lef, def, gds & standard cells view generation process (Milkyway & NDM)
- Experience using Synopsys (ICC/ICC-II/Fusion Compiler ,DC,PT) tools ,Cadence (soce/innovus, RC/genus) design tools.
Job/Req. ID: 4719
Company: Synopsys
Location: Bangalore, KA
Job Category: VLSI/Semiconductor Engineering
Do you want Job alerts on your Phone? Join our WhatsApp/Telegram Group
