WLAN Phy (RTL) Design Engineer | Qualcomm Job | Bangalore, KA

September 23, 2024

Job description:

Qualcomm’s Bangalore WLAN PHY (Baseband) team is seeking VLSI Digital Design Engineers to lead IP development for the latest WiFi standards.

WLAN PHY team, comprised of highly passionate and seasoned domain experts, prides itself on years of experience in taking WLAN PHY designs from concept to silicon independently.
WLAN PHY team is responsible for delivering the end-to-end Tx/Rx DSP chains – all the way from antenna samples post ADC to raw bits for upper layers and on the reverse path from raw bits to DAC. The team specializes in working with challenges of practical high-speed wireless communication systems and finding innovative solutions to counter them.
The team works extensively on typical signal processing functions like filters, matrix transformations (e.g.: QR, Cholesky decomposition), channel estimation, equalization (MMSE, MRC, ML), decoders/encoders (e.g.: LDPC, Viterbi) , demodulators, FFT etc. on a day-to-day basis, and contributes to the development/ enhancement/ evaluation of signal processing algorithms to cater to new requirements.

Looking for a candidate with 1 to 3 years of hands-on experience in micro-architecting and developing complex IPs.
Expertise in digital design, VLSI concepts, and experience in creating power/area-efficient IPs across multiple clock domains are essential.
Proficiency in RTL coding and familiarity with RTL QA flows such as PLDRC, CDC, and CLP (optional) is expected.
Candidates should be capable of proposing design alternatives to meet area/power/performance specifications and presenting these options for review.
Experience in leading, guiding, or managing junior team members is advantageous.
Repeated success in taking IP designs from requirements to silicon is required.
While not mandatory, having developed IPs for wireless technologies (WLAN, LTE, NR, BT, UWB, etc.) or past HLS experience would be beneficial.
Must have: Proficient in Verilog RTL coding, uArch, CDC check, PLDRC, Timing constraints, Python/Perl. Experience in design/debugging complex data-path/control-path IPs. Good communication, analytical & leadership skills.
Good to have: System Verilog, Visio, Knowledge of signal processing concepts/algorithms and Wi-Fi standards (802.11a/b/g/n/ac/ax), experience with HLS.