Job description:
Synopsys is hiring for the post of Test & Validation Engineer.
Responsibilities:
- Work on projects or processes focused on defined components within your area of responsibility.
- Apply a practical understanding of organizational policies and procedures to resolve diverse issues in the functional area.
- Write and review test plans, test cases, and conduct benchmarks to validate complex tool features using formal verification.
- Diagnose, troubleshoot, and automate the testing of EDA tools within the organization.
- Analyze and maintain daily regression runs, resolving and addressing any failures to ensure system performance and reliability.
Qualifications:
- Education: Bachelor of Science in Electrical Engineering (BSEE) with 2+ years of experience or Master of Science in Electrical Engineering (MSEE) with ~1 year of experience.
- Technical skills:
- Solid foundation in digital electronics.
- Experience coding in HDL languages such as Verilog, VHDL, or System Verilog.
- Familiarity with formal verification concepts, including Formal Property Verification (FPV), simulation, and writing SystemVerilog Assertions (SVA).
- Knowledge of coverage metrics and simulation techniques.
- Proficiency in scripting languages like Python or Perl, with experience in developing automation for projects.
- Skills in writing test plans, creating test cases, and running benchmark designs to validate tool features using formal methodologies.
- Ability to review, resolve, and maintain daily regressions and troubleshoot benchmark failures.
Job/Req. ID: 7102
Company: Synopsys
Location: Bangalore, KA
Job Type: Full-Time
Job Category: Electrical Engineering
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