Job description:
AMD is hiring for the post of Physical Design Engineer. This position is for a physical design engineer in AMD’s Radeon Technology Group working on next generation graphics processors.
Job duties and responsibilities:
- Responsibilities include Block and/or Chip Level Floor planning, FC level Clock Routing, Bump Routing, RDL layer Routing, Physical Verification, Signoff checks.
- Understanding of Placement, Optimization, Clock tree synthesis, Routing, Parasitic Extraction, IR drop analysis, Physical Verification and Sign Off flows.
- Flow automation using perl/tcl programming.
Requirements:
- Experience in ASIC Physical Design from RTL to GDSII.
- Tasks include full chip level physical verification, clock routing, Power/IO Bump planning, RDL routing.
- Experienced in Layout design, Synthesis, Placement, Clock tree synthesis, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, Physical Verification and Sign Off.
- Strong communication and presentation skill, experience in working with global team
- Hands on experience in taping out 3nm, 5nm, 7nm, SOC design.
- Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics tool set.
- Must be a self-starter, and be able to independently and efficiently drive tasks to completion
- Ability to provide mentorship and guidance to junior engineers, and be an effective team player
Job/Req. ID: 54763
Company: AMD
Location: Bangalore, KA
Job Category: VLSI Engineering
Join all India VLSI Jobs Telegram Group
