Job description:
Google is conducting an interview for the post of SOC Power Estimation Engineer.
Responsibilities:
- Drive pre-silicon power estimation and analysis using power estimation tools both at Register-Transfer Level (RTL) and Netlist level.
- Develop methodologies around power estimation tools and incorporate best practices to improve the power estimation.
- Drive Power estimation and what-if analysis for IP(s) and SubSystem(s) and drive closure of projections vs targets gaps.
- Analyze power estimation reports to identify power-saving opportunities and influence both the physical design aspect and the u-arch design aspects of the design for power reduction.
- Collaborate with the Arch Design team to define the right definition of scenarios and operating conditions to estimate the use-case power for the IP which reflects the real world usage of the IP.
Minimum qualifications:
- Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience
- 2 years of experience with low power RTL and physical design techniques.
- Experience with scripting languages (e.g., Python, Perl).
Preferred qualifications:
- Experience in System on a Chip (SoC) architecture, power management architecture, clocking architecture.
- Experience with RTL level power estimation/analysis tools.
- Ability to work separately and as part of a team.
- Excellent problem-solving and investigative skills.
- Excellent communication and teamwork skills.
Job/Req. ID: N/A
Company: Google
Location: Bangalore, KA
Job Category: VLSI or Electrical or Computer Science Engineering
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