Job description:
Alternate Job titles:
- Layout Design Engineer
- Analog Layout Engineer
Duties and responsibilities:
As an ideal candidate, you are passionate about technology and innovation, eager to dive into the world of chip design and integration. You are a proactive learner, ready to adapt to rapid changes in technology and eager to contribute to cutting-edge projects. Your foundational knowledge in device physics and layout concepts equips you to tackle challenges in developing the next generation of DDR, HBM, and UCIe PHY IPs. You possess a keen eye for detail, ensuring that your work meets high-quality standards. Your ability to communicate effectively, both in writing and verbally, allows you to collaborate seamlessly with your team. You are open to learning and growing in a dynamic environment, making you a valuable asset to our team.
- Hands-on layout development for next-generation DDR, HBM, and UCIe IPs.
- Creating layout floorplans, routing, and performing physical verifications to meet quality requirements.
- Collaborating with design engineers to ensure layout designs meet performance, power, and area targets.
- Implementing layout matching techniques, ESD, latch-up, EMIR, and DFM considerations.
- Adhering to deep submicron effects and floorplan techniques in CMOS and FinFET technologies.
- Participating in design reviews and providing feedback to improve design quality and efficiency.
The Impact you will have:
- Contributing to the development of cutting-edge IP that powers innovations in technology.
- Ensuring high-quality layout designs that meet stringent performance and reliability standards.
- Helping accelerate the integration of advanced capabilities into SoCs, reducing time-to-market.
- Enhancing the overall efficiency and effectiveness of the design process through meticulous layout work.
- Supporting the creation of differentiated products that stand out in the market.
- Playing a crucial role in maintaining Synopsys’ leadership in technology and innovation.
Requirements:
- Bachelor’s or Master’s degree in a relevant field (BTech/MTech).
- 0 to 1 year of relevant experience in layout design.
- Basic understanding of device physics and layout concepts.
- Knowledge of layout matching techniques, ESD, latch-up, EMIR, and DFM.
- Familiarity with deep submicron effects and floorplan techniques in CMOS and FinFET technologies.
Personal traits:
- Proactive and eager to learn new technologies and concepts.
- Detail-oriented with a strong focus on quality and precision.
- Effective communicator with good written and verbal skills.
- Collaborative team player who thrives in a dynamic environment.
- Adaptable and open to feedback, continuously seeking to improve.
About the team:
You will be joining a dedicated team of engineers focused on developing next-generation DDR, HBM, and UCIe PHY IPs. Our team values collaboration, innovation, and excellence.
Job/Req. ID: 8236
Company: Synopsys
Location: Bangalore, KA
Job Category: VLSI Engineering
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