Job description:
PierSight is conducting an internship for Engineers in Ahmedabad.
Job duties and responsibilities:
- Create well written block level design documentation
- Write testbench and sequences in SystemVerilog
Requirements:
- 0-1 years of hands-on experience in implementing designs on FPGA
- Strong expertise in RTL coding of complex designs using VHDL/Verilog/SV
- Knowledge in all aspects of FPGA design; constraint definition, synthesis, floor planning, P&R, Timing closure
- Familiarity with lab equipment
- Familiarity with interface protocols
- Knowledge of latest FPGA architectures
- Exposure to scripting languages
Preferred experience:
- Hands on experience with FPGA design suite Libero
- Tcl/perl/python scripting languages
- Good hardware and software debugging skills
- Knowledge on running quality checks such as CDC
- Knowledge on synthesis, static timing analysis concepts
- Knowledge on FPGA Hardware design is added advantage
Job/Req. ID: N/A
Company: PierSight
Location: Ahmedabad
Job Category: VLSI Engineering
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