Synopsys Is Looking for Formal Verification Interns (ID: 8583)

Description:

Synopsys is inviting applications for the post of Formal Verification Intern.

Duties and responsibilities:

Formal Verification Engineer at Synopsys, you will be responsible for formally verifying complex design IPs. Synopsys IP Group has a strong formal verification methodology that enables hardware verification engineers to use FV tools and techniques successfully on complex and/or critical RTL logic. The job involves very close interaction with the designers, architects, verification engineers and Synopsys’s Tool Development Group to drive verification projects.

• Help decide on the best applications of formal verification techniques to various parts of the design.
• Review functional and micro-architectural specifications, define the scope for formal verification, and create high-quality formal verification testplans to sign-off on the corresponding design implementation.
• Build formal verification testbenches, code assertions and constraints, and apply abstraction techniques to converge the targeted properties or to achieve reasonable proof-depth.
• Apply formal coverage techniques for analysing over-constraints and for measuring functional coverage.

Requirements:

• Pursuing or completed BTech/ MTech degree
• Good understanding of hardware micro-architecture and design
• Proficiency in HDLs like Verilog, SystemVerilog
• Familiarity with SystemVerilog Assertions (SVA) and basic concepts of formal property verification
• Good debugging and problem-solving skills
• Scripting knowledge (Python/Perl/shell)
• Good interpersonal and communication skills and dream to work as a great team member

Skills required:

• Academic projects related to formal verification or digital design verification
• Exposure to formal verification tools like VCFormal, Jasper, Yosys etc
• Knowledge of protocols like AXI, CHI, PCIe, DDR, etc