Job description:
Google is conducting an interview for the post of ASIC DFT Engineer.
Duties and responsibilities:
In this role, you will work with a team of Design for Testing (DFT) Engineers, working closely with Register-Transfer Level (RTL) and Physical Designer Engineers.
- Work on Subsystem level DFT scan, Memory Built-In Self Test (MBIST) architecture with multiple voltage, power domains.
- Write basic scripts to automate the DFT flow.
- Develop tests that can be used for production in the Automatic Test Equipment (ATE) flow.
Minimum qualifications:
- Bachelor’s degree in Electrical or Electronics Engineering, or equivalent practical experience.
- 3 years of experience in DFT methodologies.
- Experience with DFT Electronic Design Automation (EDA) tools like Tessent.
- Experience with Automatic Test Pattern Generation (ATPG), Low Power designs, Built-In Self Test (BIST), Joint Test Action Group (JTAG), Internal Joint Test Action Group (IJTAG) tools and flow.
Preferred qualifications:
- Experience architecting/developing DFT flows and methodologies.
- Experience in collaborating with Design, Physical Design (PD) and Static Timing Analysis (STA) teams.
- Excellent scripting skills in languages like Python and TCL.
Job/Req. ID: N/A
Company: Google
Location: Bangalore, KA
Job Category: VLSI Engineering
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