ASIC Engineer, Devices and Services Job In Bangalore at Google

Job description:

Google is hiring ASIC Engineers for their Bangalore office.

About the job

As a part of the Google Silicon Platforms team, you will work on the verification of the architecture of Google’s SOC offerings. You will collaborate with hardware architects and design engineers for functional and performance verification of the infrastructure IP, interconnects, caches, memory management and system services. You also work on developing high performance Verification IPs for protocols supported by our SOCs, and collaborate in the deployment of the verification stack across a set of IPs. Our approach to building systems is based on scalability. Your work will include building and verifying a generalized system topology abstractions, and developing the associated methodologies and tools needed to solve the problem.

Duties and responsibilities:

• Plan and execute the verification of the next generation configurable Infrastructure IPs, interconnects and memory subsystems.
• Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology.
• Develop cross language tools and scalable verification methodologies.
• Identify and write all types of coverage measures for stimulus and corner-cases.
• Debug tests with design engineers to deliver blocks and subsystems. Close coverage measures to identify verification holes and to show progress towards tape-out.

Minimum qualifications:

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science or equivalent practical experience.
• Experience verifying digital systems using standard IP components/interconnects (i.e., microprocessor cores, hierarchical memory subsystems) and experience with scripting languages and software development frameworks.
• Experience verifying digital logic at RTL level using SystemVerilog or C/C++.
• Experience with performance verification of SOCs, pre-Silicon analysis and post-Silicon correlation and with building verification methodologies that span simulation, emulation and FPGA prototypes.
• Experience creating and using verification components and environments in standard verification methodology, Design Verification Test, SystemVerilog, Verilog, Computer Architecture, System On a Chip and Python.

Preferred qualifications:

• Master’s degree or PhD, in Electrical Engineering or Computer Science or equivalent practical experience.
• Experience in one or more of the following: Caches Hierarchies, Coherency, Memory Consistency Models, DDR/LPDDR, PCIe, Packet Processors, Security, Clock and Power Controllers.
• Experience with Interconnect Protocols (e.g., AHB, AXI, ACE, CHI, CCIX, CXL).