Job description:
L&T Semiconductor Technologies is looking for Physical Verification Engineers.
Duties and responsibilities:
- Expertise in physical verification of SoC/Full-chip-level and/or block-level DRC, Experience and understanding of all phases of the IC design process from RTL->GDS2
- LVS, ERC/PERC, DFM, OPC, Tape Out process
- Preferably worked on 5nm/7nm/12nm/14nm/16nm/22nm nodes at the major foundries
- Experience in developing sign-off methodology/flow to and supporting a larger team
- Experience in debugging LVS issues at chip-level with complex analog-mixed signal Ips
- Experience with design using low-power implementation (level-shifters, isolation cells, power domain/islands, substrate isolation etc.)
- Experience in physical verification of I/O Ring, corner cells, seal ring, RDL routing, bumps and other full-chip components
- Good understanding of CMOS/FinFET process and circuit design, base layer related DRCs, ERC rules, latch-up etc.
- Experience with ERC rules, PERC rules, ESD rules has an added advantage
- Expert in EDA Tools: Mentor (Calibre), Synopsys (ICV)/ Cadence (Pegasus)
- Strong communication skills, problem solving and analytical skills
Job/Req. ID: N/A
Company: L&T Semiconductor Technologies
Location: Bangalore, KA
Job Category: VLSI Engineering
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