Job description:
L&T Semiconductor Technologies is looking for Chip Layout/Floor Planning Engineer.
Duties and requirements:
This position is for a senior-level physical design engineer who will work on Floor planning/Bump Planning/ Pin assignments /Feed through/ LFU Optimization/ Work hands-on to solve critical design and execution issues related to physical verification/implementation and sign-off.
- Strong hands-on experience with Chip Level / Sub-chip level floor planning,
- Performing floor-planning and routing studies and implementation at block and full-chip level
- Push down the top-level floorplan and clock to Partition.
- partition, pin assignment, Power planning, IO/Bump Planning, Pad Ring Creation, Die File Creation, RDL Routing, working with Package Team for Optimize the Bumps.
- Closely working with Package team and reaching Die file milestones
Job/Req. ID: N/A
Company: L&T Semiconductor Technologies
Location: Bangalore, KA
Job Category: VLSI Engineering
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