Job description:
Synopsys is conducting an internship for Engineers.
Duties and responsibilities:
- Writing constrained-random System Verilog test benches using UVM/VMM.
- Examining functional, assertions and code coverage.
- Debugging RTL and gate-level simulations failures.
- Testing products and flows to ensure quality and reliability.
- Verifying fixed issues to confirm effective resolution.
- Collaborating with the engineering team to identify and address technical challenges.
- Documenting test cases, procedures, and results for transparency and learning.
- Providing feedback for continuous tool and process improvements
- Participating in team discussions to brainstorm solutions and share innovative ideas.
Requirements:
- Currently pursuing / recent graduate of B-Tech or M-Tech in Electronic Engineering, Computer Science, or a related field (penultimate or final year is preferred).
- Strong analytical and problem-solving skills.
- Basic knowledge of digital electronics concepts.
- Excellent communication skills.
- Meticulous attention to detail.
- Ability to work collaboratively in a team environment.
- Proactive attitude and eagerness to learn.
Key program facts:
- Program Length: 12 months
- Working Model: On-site
- Type of Internship: Industrial Placement
- Full-Time/Part-Time: Full-time
- Start Date: July/August 2025
Job/Req. ID: 10702
Company: Synopsys
Location: Bangalore, KA
Job Category: VLSI Engineering
Join all India VLSI Jobs channel
